Colin Drewes
PhD Student
Stanford
MS Computer Science '22
BS Computer Science '21
University of California San Diego
drewes at cs.stanford.edu
I am a third year Computer Science PhD student at Stanford University working with Professor Subhasish Mitra on scalable machine learning inference architectures.
I am also interested in the effect of Bias Temperature Instability, a form of transistor degradation, on the security of hardware systems. Advised by Professor Dustin Richmond, Ryan Kastner, and David Kohlbrenner, I explored the feasibility of this side-channel in cloud deployments of Field Programmable Gate Arrays (FPGAs). Our recent results demonstrated that sensitive data loaded into a cloud-FPGA's routing at runtime is imprinted in the device via variable transistor wear, and this side-channel can be exploited by a future user of the device through the instantiation of a precise timing sensor in its programmable fabric.
This work builds off the results of my work at the University of California San Diego, where I completed my BS and MS degree. My research focused on power side-channels in cloud FPGAs but later pivoted to the transistor side-channels being explored currently. I was advised by Professor Ryan Kastner and Dustin Richmond and my thesis was supervised by Professor Ryan Kastner, Deian Stefan, and Dean Tullsen.
I am a recipient of, and have received financial support from, the Qualcomm Innovation Fellowship.
SCCM 23: Pentimento: Data Remanence in Cloud FPGAs
ISFPGA 23: Maximizing Side-Channel Recovery in Time-to-Digital Converters
SCCM 22: Open Source Time-to-Digital Converter
DAC 21: Classifying Computations on Multi-Tenant FPGAs
Colin Drewes, Tyler Sheaves, Olivia Weng, Keegan Ryan, William Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond,Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters, ACM Transactions on Reconfigurable Technology and Systems, June 2024
Colin Drewes, Olivia Weng, Keegan Ryan, William Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond, Turn on, Tune in, Listen up: Maximizing Channel Capacity in Time-to-Digital Converters, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA), February 2023 [Best Paper Candidate]
Mustafa Gobulukoglu, Colin Drewes, William Hunter, Ryan Kastner, and Dustin Richmond, Classifying Computations on Multi-Tenant FPGAs, Design Automation Conference (DAC), December 2021
2024 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)
2023 IEEE 31th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
2021 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
2021 IEEE International Conference on Computer-Aided Design (ICCAD)
Winter 2022: CSE 160 - Introduction to Parallel Computing (Professor Ryan Kastner)
Fall 2021: CSE 101 - Design and Analysis of Algorithms (Professor Miles Jones)
Writing/Notes
A Reconfigurable RISC-V Co-ProcessorGlobally Irreversible Locally Reversible
Managing Xilinx IP in Chisel
Tcl Scripting for Pentimenti Attacks
Programming Soft-processors from Linux Kernel