Colin Drewes

PhD Student | Stanford | drewes at cs.stanford.edu
MS Computer Science '22, BS Computer Science '21 | UC San Diego

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I am a fifth year Computer Science PhD student at Stanford University working with Professor Subhasish Mitra on scalable machine learning inference architectures.

I am also interested in the effect of Bias Temperature Instability, a form of transistor degradation, on the security of hardware systems. Advised by Professor Dustin Richmond, Ryan Kastner, and David Kohlbrenner, I explored the feasibility of this side-channel in cloud deployments of Field Programmable Gate Arrays (FPGAs). Our recent results demonstrated that sensitive data loaded into a cloud-FPGA's routing at runtime is imprinted in the device via variable transistor wear, and this side-channel can be exploited by a future user of the device through the instantiation of a precise timing sensor in its programmable fabric.

This work builds off my work at UC San Diego, where I completed my BS and MS. My research focused on power side-channels in cloud FPGAs but later pivoted to the transistor side-channels being explored currently. I was advised by Professor Ryan Kastner and Dustin Richmond; my thesis was supervised by Professor Ryan Kastner, Deian Stefan, and Dean Tullsen.

I am a recipient of the Qualcomm Innovation Fellowship.

I have served as an external reviewer for CCS '24, FPGA '24, FCCM '20, '22, '23, and ICCAD '21.

I have served as a teaching assistant for Stanford CS 244: Advanced Topics in Networking (Spring 2024), UCSD CSE 160: Introduction to Parallel Computing (Winter 2022), and UCSD CSE 101: Design and Analysis of Algorithms (Fall 2021).