Colin Drewes

self
PhD Student
Stanford
MS Computer Science '22, BS Computer Science '21
University of California, San Diego

CV
Presentations
Publications
Selected Projects
Teaching

Interests

Computer Architecture, Distributed Systems, Computer Security,
FPGA Security, Cryptography

News

(2/12/23)1st: "Turn on, Tune in, Listen up: Maximizing Channel Capacity in Time-to-Digital Converters" will appear as a paper in the 2023 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA).
(10/6/22): Recognized by Kastner Research Group for MS Research Award and my three years of work.
(9/26/22): After four years at UCSD, I have moved to Stanford to complete my PhD.
(6/20/22): Received 2022 UCSD Department of Computer Science and Engineering MS Research Award.
(5/18/22)1st,,: Presented our open-source TDC implementation at the Workshop on Security for Custom Computing Machines. (5/6/22)1st,: My master thesis "Next Generation Cloud-FPGA Side-Channels" was accepted by my Committee Chair, Prof. Ryan Kastner, and Committee Members, Prof. Dean Tullsen and Prof. Deian Stefan (UCSD).
(2/11/22): Recognized by Kastner Research Group for DAC paper and presentation.
(12/5/21)2nd,,: "Classifying Computations on Multi-Tenant FPGAs" appeared as a paper at the 2021 Design and Automation Coference (DAC).
(9/1/21)1st,,: Presented early stage Time-to-Digitial Converter research at the UC Santa Barbara Arch Lab.
(5/9/21)1st,,: "A Tunable Dual-Edge Time-to-Digital Converter: appeared as an extended abstract at the IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).
(2/28/21)2nd: "Classifying Computations on Multi-Tenant FPGAs" appeared as a poster at the 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA).
(1st, 2nd, 3rd,...) = my authorship role. () = I presented this work. () = pdf available.

Contact

drewes at cs.stanford.edu