MS Computer Science '22
BS Computer Science '21
University of California San Diego
drewes at cs.stanford.edu
I am a second year Computer Science PhD student at Stanford University interested in operating/distributed systems and computer architecture. I work with Professor Caroline Trippel, Keith Winstein, and John Ousterhout. Currently we are developing a reprogrammable Network Interface Card capable of implementing a diverse range of transport protocols entirely in hardware. Early work on this project has focused on deploying the Homa transport protocol on a Field Programmable Gate Array.
I am also interested in the effect of Bias Temperature Instability, a form of transistor degradation, on the security of hardware systems. Advised by Professor Dustin Richmond, Ryan Kastner, and David Kohlbrenner, I am exploring the feasibility of this side-channel in cloud deployments of Field Programmable Gate Arrays (FPGAs). Our recent results have demonstrated that sensitive data loaded into a cloud-FPGA's routing at runtime is imprinted in the device via variable transistor wear, and this side-channel can be exploited by a future user of the device through the instantiation of a precise timing sensor in its programmable fabric.
This work builds off the results of my work at the University of California San Diego, where I completed my BS and MS degree. My research focused on power side-channels in cloud FPGAs but later pivoted to the transistor side-channels being explored currently. I was advised by Professor Ryan Kastner and Dustin Richmond and my thesis was supervised by Professor Ryan Kastner, Deian Stefan, and Dean Tullsen.
I am financially supported by Professor Caroline Trippel, and Keith Winstein, as well as the Qualcomm Innovation Fellowship.
ISFPGA 23: Maximizing Side-Channel Recovery in Time-to-Digital Converters
SCCM 22: Open Source Time-to-Digital Converter
DAC 21: Classifying Computations on Multi-Tenant FPGAs
[Best Paper Candidate] Colin Drewes, Olivia Weng, Keegan Ryan, William Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond, Turn on, Tune in, Listen up: Maximizing Channel Capacity in Time-to-Digital Converters, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA), February 2023
Mustafa Gobulukoglu, Colin Drewes, William Hunter, Ryan Kastner, and Dustin Richmond, Classifying Computations on Multi-Tenant FPGAs, Design Automation Conference (DAC), December 2021
2023 IEEE 31th Annual International Symposium on Field-Programmable Custom Computing Machines
2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines
2021 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines
2021 IEEE International Conference on Computer-Aided Design
Fall 2021: CSE 101 - Design and Analysis of Algorithms (Instructor: Professor Miles Jones)
Writing/NotesA Reconfigurable RISC-V Co-Processor
Globally Irreversible Locally Reversible
Managing Xilinx IP in Chisel
Tcl Scripting for Pentimenti Attacks